REG(v0,		32, 0, 0, NULL)
REG(v1,		32, 1, 0, NULL)
REG(v2,		32, 2, 0, NULL)
REG(v3,		32, 3, 0, NULL)
REG(v4,		32, 4, 0, NULL)
REG(v5,		32, 5, 0, NULL)
REG(v6,		32, 6, 0, NULL)
REG(v7,		32, 7, 0, NULL)
REG(v8,		32, 8, 0, NULL)
REG(v9,		32, 9, 0, NULL)
REG(v10,	32, 10, 0, NULL)
REG(v11,	32, 11, 0, NULL)
REG(v12,	32, 12, 0, NULL)
REG(v13,	32, 13, 0, NULL)
REG(v14,	32, 14, 0, NULL)
REG(v15,	32, 15, 0, NULL)
REG(v16,	32, 16, 0, NULL)
REG(v17,	32, 17, 0, NULL)
REG(v18,	32, 18, 0, NULL)
REG(v19,	32, 19, 0, NULL)
REG(v20,	32, 20, 0, NULL)
REG(v21,	32, 21, 0, NULL)
REG(v22,	32, 22, 0, NULL)
REG(v23,	32, 23, 0, NULL)
REG(v24,	32, 24, 0, NULL)
REG(v25,	32, 25, 0, NULL)
REG(v26,	32, 26, 0, NULL)
REG(v27,	32, 27, 0, NULL)
REG(v28,	32, 28, 0, NULL)
REG(v29,	32, 29, 0, NULL)
REG(v30,	32, 30, 0, NULL)
REG(v31,	32, 31, 0, NULL)
REG(v32,	32, 32, 0, NULL)
REG(v33,	32, 33, 0, NULL)
REG(v34,	32, 34, 0, NULL)
REG(v35,	32, 35, 0, NULL)
REG(v36,	32, 36, 0, NULL)
REG(v37,	32, 37, 0, NULL)
REG(v38,	32, 38, 0, NULL)
REG(v39,	32, 39, 0, NULL)
REG(v40,	32, 40, 0, NULL)
REG(v41,	32, 41, 0, NULL)
REG(v42,	32, 42, 0, NULL)
REG(v43,	32, 43, 0, NULL)
REG(v44,	32, 44, 0, NULL)
REG(v45,	32, 45, 0, NULL)
REG(v46,	32, 46, 0, NULL)
REG(v47,	32, 47, 0, NULL)
REG(v48,	32, 48, 0, NULL)
REG(v49,	32, 49, 0, NULL)
REG(v50,	32, 50, 0, NULL)
REG(v51,	32, 51, 0, NULL)
REG(v52,	32, 52, 0, NULL)
REG(v53,	32, 53, 0, NULL)
REG(v54,	32, 54, 0, NULL)
REG(v55,	32, 55, 0, NULL)
REG(v56,	32, 56, 0, NULL)
REG(v57,	32, 57, 0, NULL)
REG(v58,	32, 58, 0, NULL)
REG(v59,	32, 59, 0, NULL)
REG(v60,	32, 60, 0, NULL)
REG(v61,	32, 61, 0, NULL)
REG(v62,	32, 62, 0, NULL)
REG(v63,	32, 63, 0, NULL)
REG(v64,	32, 64, 0, NULL)
REG(v65,	32, 65, 0, NULL)
REG(v66,	32, 66, 0, NULL)
REG(v67,	32, 67, 0, NULL)
REG(v68,	32, 68, 0, NULL)
REG(v69,	32, 69, 0, NULL)
REG(v70,	32, 70, 0, NULL)
REG(v71,	32, 71, 0, NULL)
REG(v72,	32, 72, 0, NULL)
REG(v73,	32, 73, 0, NULL)
REG(v74,	32, 74, 0, NULL)
REG(v75,	32, 75, 0, NULL)
REG(v76,	32, 76, 0, NULL)
REG(v77,	32, 77, 0, NULL)
REG(v78,	32, 78, 0, NULL)
REG(v79,	32, 79, 0, NULL)
REG(v80,	32, 80, 0, NULL)
REG(v81,	32, 81, 0, NULL)
REG(v82,	32, 82, 0, NULL)
REG(v83,	32, 83, 0, NULL)
REG(v84,	32, 84, 0, NULL)
REG(v85,	32, 85, 0, NULL)
REG(v86,	32, 86, 0, NULL)
REG(v87,	32, 87, 0, NULL)
REG(v88,	32, 88, 0, NULL)
REG(v89,	32, 89, 0, NULL)
REG(v90,	32, 90, 0, NULL)
REG(v91,	32, 91, 0, NULL)
REG(v92,	32, 92, 0, NULL)
REG(v93,	32, 93, 0, NULL)
REG(v94,	32, 94, 0, NULL)
REG(v95,	32, 95, 0, NULL)
REG(v96,	32, 96, 0, NULL)
REG(v97,	32, 97, 0, NULL)
REG(v98,	32, 98, 0, NULL)
REG(v99,	32, 99, 0, NULL)
REG(v100,	32, 100, 0, NULL)
REG(v101,	32, 101, 0, NULL)
REG(v102,	32, 102, 0, NULL)
REG(v103,	32, 103, 0, NULL)
REG(v104,	32, 104, 0, NULL)
REG(v105,	32, 105, 0, NULL)
REG(v106,	32, 106, 0, NULL)
REG(v107,	32, 107, 0, NULL)
REG(v108,	32, 108, 0, NULL)
REG(v109,	32, 109, 0, NULL)
REG(v110,	32, 110, 0, NULL)
REG(v111,	32, 111, 0, NULL)
REG(v112,	32, 112, 0, NULL)
REG(v113,	32, 113, 0, NULL)
REG(v114,	32, 114, 0, NULL)
REG(v115,	32, 115, 0, NULL)
REG(v116,	32, 116, 0, NULL)
REG(v117,	32, 117, 0, NULL)
REG(v118,	32, 118, 0, NULL)
REG(v119,	32, 119, 0, NULL)
REG(v120,	32, 120, 0, NULL)
REG(v121,	32, 121, 0, NULL)
REG(v122,	32, 122, 0, NULL)
REG(v123,	32, 123, 0, NULL)
REG(v124,	32, 124, 0, NULL)
REG(v125,	32, 125, 0, NULL)
REG(v126,	32, 126, 0, NULL)
REG(v127,	32, 127, 0, NULL)
REG(v128,	32, 128, 0, NULL)
REG(v129,	32, 129, 0, NULL)
REG(v130,	32, 130, 0, NULL)
REG(v131,	32, 131, 0, NULL)
REG(v132,	32, 132, 0, NULL)
REG(v133,	32, 133, 0, NULL)
REG(v134,	32, 134, 0, NULL)
REG(v135,	32, 135, 0, NULL)
REG(v136,	32, 136, 0, NULL)
REG(v137,	32, 137, 0, NULL)
REG(v138,	32, 138, 0, NULL)
REG(v139,	32, 139, 0, NULL)
REG(v140,	32, 140, 0, NULL)
REG(v141,	32, 141, 0, NULL)
REG(v142,	32, 142, 0, NULL)
REG(v143,	32, 143, 0, NULL)
REG(v144,	32, 144, 0, NULL)
REG(v145,	32, 145, 0, NULL)
REG(v146,	32, 146, 0, NULL)
REG(v147,	32, 147, 0, NULL)
REG(v148,	32, 148, 0, NULL)
REG(v149,	32, 149, 0, NULL)
REG(v150,	32, 150, 0, NULL)
REG(v151,	32, 151, 0, NULL)
REG(v152,	32, 152, 0, NULL)
REG(v153,	32, 153, 0, NULL)
REG(v154,	32, 154, 0, NULL)
REG(v155,	32, 155, 0, NULL)
REG(v156,	32, 156, 0, NULL)
REG(v157,	32, 157, 0, NULL)
REG(v158,	32, 158, 0, NULL)
REG(v159,	32, 159, 0, NULL)
REG(v160,	32, 160, 0, NULL)
REG(v161,	32, 161, 0, NULL)
REG(v162,	32, 162, 0, NULL)
REG(v163,	32, 163, 0, NULL)
REG(v164,	32, 164, 0, NULL)
REG(v165,	32, 165, 0, NULL)
REG(v166,	32, 166, 0, NULL)
REG(v167,	32, 167, 0, NULL)
REG(v168,	32, 168, 0, NULL)
REG(v169,	32, 169, 0, NULL)
REG(v170,	32, 170, 0, NULL)
REG(v171,	32, 171, 0, NULL)
REG(v172,	32, 172, 0, NULL)
REG(v173,	32, 173, 0, NULL)
REG(v174,	32, 174, 0, NULL)
REG(v175,	32, 175, 0, NULL)
REG(v176,	32, 176, 0, NULL)
REG(v177,	32, 177, 0, NULL)
REG(v178,	32, 178, 0, NULL)
REG(v179,	32, 179, 0, NULL)
REG(v180,	32, 180, 0, NULL)
REG(v181,	32, 181, 0, NULL)
REG(v182,	32, 182, 0, NULL)
REG(v183,	32, 183, 0, NULL)
REG(v184,	32, 184, 0, NULL)
REG(v185,	32, 185, 0, NULL)
REG(v186,	32, 186, 0, NULL)
REG(v187,	32, 187, 0, NULL)
REG(v188,	32, 188, 0, NULL)
REG(v189,	32, 189, 0, NULL)
REG(v190,	32, 190, 0, NULL)
REG(v191,	32, 191, 0, NULL)
REG(v192,	32, 192, 0, NULL)
REG(v193,	32, 193, 0, NULL)
REG(v194,	32, 194, 0, NULL)
REG(v195,	32, 195, 0, NULL)
REG(v196,	32, 196, 0, NULL)
REG(v197,	32, 197, 0, NULL)
REG(v198,	32, 198, 0, NULL)
REG(v199,	32, 199, 0, NULL)
REG(v200,	32, 200, 0, NULL)
REG(v201,	32, 201, 0, NULL)
REG(v202,	32, 202, 0, NULL)
REG(v203,	32, 203, 0, NULL)
REG(v204,	32, 204, 0, NULL)
REG(v205,	32, 205, 0, NULL)
REG(v206,	32, 206, 0, NULL)
REG(v207,	32, 207, 0, NULL)
REG(v208,	32, 208, 0, NULL)
REG(v209,	32, 209, 0, NULL)
REG(v210,	32, 210, 0, NULL)
REG(v211,	32, 211, 0, NULL)
REG(v212,	32, 212, 0, NULL)
REG(v213,	32, 213, 0, NULL)
REG(v214,	32, 214, 0, NULL)
REG(v215,	32, 215, 0, NULL)
REG(v216,	32, 216, 0, NULL)
REG(v217,	32, 217, 0, NULL)
REG(v218,	32, 218, 0, NULL)
REG(v219,	32, 219, 0, NULL)
REG(v220,	32, 220, 0, NULL)
REG(v221,	32, 221, 0, NULL)
REG(v222,	32, 222, 0, NULL)
REG(v223,	32, 223, 0, NULL)
REG(v224,	32, 224, 0, NULL)
REG(v225,	32, 225, 0, NULL)
REG(v226,	32, 226, 0, NULL)
REG(v227,	32, 227, 0, NULL)
REG(v228,	32, 228, 0, NULL)
REG(v229,	32, 229, 0, NULL)
REG(v230,	32, 230, 0, NULL)
REG(v231,	32, 231, 0, NULL)
REG(v232,	32, 232, 0, NULL)
REG(v233,	32, 233, 0, NULL)
REG(v234,	32, 234, 0, NULL)
REG(v235,	32, 235, 0, NULL)
REG(v236,	32, 236, 0, NULL)
REG(v237,	32, 237, 0, NULL)
REG(v238,	32, 238, 0, NULL)
REG(v239,	32, 239, 0, NULL)
REG(v240,	32, 240, 0, NULL)
REG(v241,	32, 241, 0, NULL)
REG(v242,	32, 242, 0, NULL)
REG(v243,	32, 243, 0, NULL)
REG(v244,	32, 244, 0, NULL)
REG(v245,	32, 245, 0, NULL)
REG(v246,	32, 246, 0, NULL)
REG(v247,	32, 247, 0, NULL)
REG(v248,	32, 248, 0, NULL)
REG(v249,	32, 249, 0, NULL)
REG(v250,	32, 250, 0, NULL)
REG(v251,	32, 251, 0, NULL)
REG(v252,	32, 252, 0, NULL)
REG(v253,	32, 253, 0, NULL)
REG(v254,	32, 254, 0, NULL)
REG(v255,	32, 255, 0, NULL)