/* platform-specific */
#if !defined(W)
# if defined(ARCH_yasep16)
#  define W	16
# else
#  define W	32
# endif
#endif
REG(npc, W, 0x00, 0, NULL)
REG(r1,  W, 0x01, 0, NULL)
REG(r2,  W, 0x02, 0, NULL)
REG(r3,  W, 0x03, 0, NULL)
REG(r4,  W, 0x04, 0, NULL)
REG(r5,  W, 0x05, 0, NULL)
REG(d5,  W, 0x06, 0, NULL)
REG(a5,  W, 0x07, 0, NULL)
REG(d4,  W, 0x08, 0, NULL)
REG(a4,  W, 0x09, 0, NULL)
REG(d3,  W, 0x0a, 0, NULL)
REG(a3,  W, 0x0b, 0, NULL)
REG(d2,  W, 0x0c, 0, NULL)
REG(a2,  W, 0x0d, 0, NULL)
REG(d1,  W, 0x0e, 0, NULL)
REG(a1,  W, 0x0f, 0, NULL)
REG(r0,  W, 0x00, 0, NULL)
REG(r1,  W, 0x01, 0, NULL)
REG(r2,  W, 0x02, 0, NULL)
REG(r3,  W, 0x03, 0, NULL)
REG(r4,  W, 0x04, 0, NULL)
REG(r5,  W, 0x05, 0, NULL)
REG(r6,  W, 0x06, 0, NULL)
REG(r7,  W, 0x07, 0, NULL)
REG(r8,  W, 0x08, 0, NULL)
REG(r9,  W, 0x09, 0, NULL)
REG(r10, W, 0x0a, 0, NULL)
REG(r11, W, 0x0b, 0, NULL)
REG(r12, W, 0x0c, 0, NULL)
REG(r13, W, 0x0d, 0, NULL)
REG(r14, W, 0x0e, 0, NULL)
REG(r15, W, 0x0f, 0, NULL)