TARGETS	= $(OBJDIR)top.vhdl $(OBJDIR)top.vvp $(OBJDIR)top.fpga $(OBJDIR)s\ p\ a\ c\ e.fpga
OBJDIR	=
PREFIX	= /usr/local
DESTDIR	=
BINDIR	= $(PREFIX)/bin
SBINDIR	= $(PREFIX)/sbin
VERILOG	= iverilog
EXEEXT	=
RM	= rm -f
LN	= ln -f
MKDIR	= mkdir -m 0755 -p
INSTALL	= install


all: $(TARGETS)

top.vhdl_OBJS = $(OBJDIR)top.vhdl
top.vhdl_VFLAGS = $(VFLAGSF) $(VFLAGS) -tvhdl

top.vvp_OBJS = $(OBJDIR)top.vvp
top.vvp_VFLAGS = $(VFLAGSF) $(VFLAGS)

top.fpga_OBJS = $(OBJDIR)top.fpga
top.fpga_VFLAGS = $(VFLAGSF) $(VFLAGS) -tfpga

s_p_a_c_e.fpga_OBJS = $(OBJDIR)s\ p\ a\ c\ e.fpga
s_p_a_c_e.fpga_VFLAGS = $(VFLAGSF) $(VFLAGS) -tfpga

$(OBJDIR)top.vhdl: top.v
	$(VERILOG) $(top.vhdl_VFLAGS) -o $(OBJDIR)top.vhdl top.v

$(OBJDIR)top.vvp: top.v
	$(VERILOG) $(top.vvp_VFLAGS) -o $(OBJDIR)top.vvp top.v

$(OBJDIR)top.fpga: top.v
	$(VERILOG) $(top.fpga_VFLAGS) -o $(OBJDIR)top.fpga top.v

$(OBJDIR)s\ p\ a\ c\ e.fpga: s\ p\ a\ c\ e.v
	$(VERILOG) $(s_p_a_c_e.fpga_VFLAGS) -o $(OBJDIR)s\ p\ a\ c\ e.fpga s\ p\ a\ c\ e.v

clean:
	$(RM) -- $(top.vhdl_OBJS) $(top.vvp_OBJS) $(top.fpga_OBJS) $(s_p_a_c_e.fpga_OBJS)

distclean: clean
	$(RM) -- $(TARGETS)

install: all

uninstall:

.PHONY: all clean distclean install uninstall